1. Field of the Invention
This invention generally relates to data processing systems and more specifically to the interchange of data between a mass storage controller and the main memory in such data processing systems.
2. Description of the Prior Art
A data processing system usually includes a central processing unit (CPU) which executes software instructions which are stored at addresses, or locations, in main memory. These software instructions are transferred to the CPU sequentially under the control of a program counter. The data that is processed is transferred into and out of the system by way of input/output devices, or peripheral devices such as teletypewriters, magnetic disks, magnetic tapes or line printers. Usually the data is temporarily stored in the main memory before or after the processing by the central processing unit.
In a system having a plurality of devices coupled over one or more common buses, an orderly system must be provided by which bidirectional transfer of information may be provided between such devices. This problem becomes more complicated when such devices include, for example, one or more memory units and various peripheral devices.
Various methods and apparatus are known in the prior art for interconnecting such a system. Such prior art systems range from those having common data bus paths to those which have special paths between various devices. Such systems also may include a capability for either synchronous or asynchronous operation in combination with the bus type. Some of these systems, independent of the manner in which such devices are connected or operate, require the central processor's control of any such data transfer on the bus even though, for example, the transfer may be between devices other than the central processor. In addition, these systems normally include various parity checking apparatus, priority schemes and interrupt structures. One such structural scheme is shown in U.S. Pat. No. 3,866,181. A data processing system utilizing a common asychronous communication bus is shown in U.S. Pat. No. 3,886,524. Another in which all units in the system, including the memory, are connected in parallel is shown in U.S. Pat. No. 3,710,324. The manner in which addressing is provided in such systems as well as the manner in which, for example, any one of the devices may control the data transfer is dependent upon the implementation of the system, i.e., whether there is a common bus, whether the operation thereof is synchronous or asynchronous, etc. The system's response and throughput capability are greatly dependent on those various structures. A particular structured scheme is shown in U.S. Pat. No. 3,993,981; U.S. Pat. No. 3,995,258; U.S. Pat. No. 3,997,896; U.S. Pat. No. 4,000,485; U.S. Pat. No. 4,001,790; and U.S Pat. No. 4,030,075 which describe an asynchronously operated common bus.
There are several ways to transfer data between a peripheral device and a main memory unit. Two popular methods are implemented by transferring data from/to the peripheral device through the CPU to/from main memory or directly from/to the peripheral device to/from the main memory.